1. Technical Field
The present invention relates to a DA conversion apparatus and a test apparatus.
2. Related Art
A conventional charge redistribution DA converter is known. The charge redistribution DA converter is provided with an internal capacitor array in which the capacitors are connected in a ladder formation.
The charge redistribution DA converter charges the capacitor array with an amount of charge corresponding to a standard voltage during a first half of the period of the data rate, and this is known as the “refresh mode.” During the second half of the each period of the data rate, the charge redistribution DA converter switches the connection of the capacitor array according to the input data, and this is known as the “output mode.” As a result, the charge redistribution DA converter can generate a voltage corresponding to the input data. This charge redistribution DA converter consumes less power than other types of DA converters.
Such a charge redistribution DA converter, however, causes linearity, offset, and gain errors in the output voltage because of the output capacitance. To correct these errors, the DA converter uses a complicated circuit configuration including another internal DA converter, and this increases the area of implementation. Furthermore, there is a technique for performing the gain correction or the like in a digital region, but when performing a digital calculation, the accuracy of the correction is limited by the accuracy of the DA converter.    Patent Document 1: U.S. Pat. No. 5,319,370    Patent Document 2: U.S. Pat. No. 6,144,331    Patent Document 3: U.S. Pat. No. 7,271,758    Patent Document 4: U.S. Pat. No. 5,852,415    Patent Document 5: U.S. Pat. No. 4,968,989    Patent Document 6: U.S. Pat. No. 6,215,431    Patent Document 7: U.S. Pat. No. 6,424,331